DDR2 SDRAM
In electronic engineering, DDR2 SDRAM or double-data-rate two synchronous dynamic random access memory is a random access memory technology used for high speed storage of the working data of a computer or other digital electronic device.
It is a part of the SDRAM (synchronous dynamic random access memory) family of technologies, which is one of many DRAM (dynamic random access memory) implementations, and is an evolutionary improvement over its predecessor, DDR SDRAM.
Its primary benefit is the ability to operate the external bus twice as fast as DDR SDRAM. This is achieved by improved bus signaling, and by operating the memory cells at half the clock rate (one quarter of the data transfer rate), rather than at the clock rate as in the original DDR. DDR2 memory at the same clock speed as DDR will provide the same bandwidth but markedly higher latency, providing worse performance.
Overview
Like all SDRAM implementations, DDR2 stores memory in memory cells that are activated with the use of a clock signal to synchronize their operation with an external data bus. Like DDR before it, DDR2 cells transfer data both on the rising and falling edge of the clock (a technique called double pumping). The key difference between DDR and DDR2 is that in DDR2 the bus is clocked at twice the speed of the memory cells, so four words of data can be transferred per memory cell cycle. Thus, without speeding up the memory cells themselves, DDR2 can effectively operate at twice the bus speed of DDR.
DDR2's bus frequency is boosted by electrical interface improvements, on-die termination, prefetch buffers and off-chip drivers. However, latency is greatly increased as a trade-off. The DDR2 prefetch buffer is 4 bits deep, whereas it is 2 bits deep for DDR and 8 bits deep for DDR3. While DDR SDRAM has typical read latencies of between 2 and 3 bus cycles, DDR2 may have read latencies between 4 and 6 cycles. Thus, DDR2 memory must be operated at twice the bus speed to achieve the same latency in nanoseconds.
Another cost of the increased speed is the requirement that the chips are packaged in a more expensive and more difficult to assemble BGA package as compared to the TSSOP package of the previous memory generations such as DDR and SDRAM. This packaging change was necessary to maintain signal integrity at higher speeds.[citation needed]
Power savings are achieved primarily due to an improved manufacturing process through die shrinkage, resulting in a drop in operating voltage (1.8 V compared to DDR's 2.5 V). The lower memory clock frequency may also enable power reductions in applications that do not require the highest available speed.
Specification standards
Chips and modules
For use in PCs, DDR2 SDRAM is supplied in DIMMs with 240 pins and a single locating notch. DIMMs are identified by their peak transfer capacity (often called bandwidth).
| Standard name | Memory clock | Cycle time | I/O Bus clock | Data transfers per second | Module name | Peak transfer rate |
| DDR2-400 | 100 MHz | 10 ns | 200 MHz | 400 Million | PC2-3200 | 3.200 GB/s |
| DDR2-533 | 133 MHz | 7.5 ns | 266 MHz | 533 Million | PC2-4200 | 4.264 GB/s |
| DDR2-667 | 166 MHz | 6 ns | 333 MHz | 667 Million | PC2-53001 | 5.336 GB/s |
| DDR2-800 | 200 MHz | 5 ns | 400 MHz | 800 Million | PC2-6400 | 6.400 GB/s |
| DDR2-1066 (planned) | 266 MHz | 3.75 ns | 533 MHz | 1066 Million | PC2-8500 (planned) | 8.500 GB/s |
Note: DDR2-xxx (or DDR-xxx) denotes data transfer rate, and describes raw DDR chips, whereas PC2-xxxx (or PC-xxxx) denotes theoretical bandwidth (though it is often rounded up or down), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR2 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.
1 Some manufacturers label their DDR2-667 sticks as PC2-5400 instead of PC2-5300. At least one manufacturer has reported this reflects successful testing at a faster-than standard speed.[1]
In addition to bandwidth and capacity variants, modules can
- Optionally implement ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC in their designation. PC2-4200 ECC is a PC2-4200 module with ECC.
- Be "registered", which improves signal integrity (and hence potentially clock speed and physical slot capacity) by electrically buffering the signals at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, whereas non-registered (a.k.a. "unbuffered") RAM may be identified by an additional U in the designation. PC2-4200R is a registered PC2-4200 module, PC2-4200R ECC is the same module but with additional ECC.
Note: registered and unbuffered SDRAM generally cannot be mixed on the same channel.
Debut
DDR2 was introduced in the second quarter of 2003 at two initial speeds: 200 MHz (referred to as PC2-3200) and 266 MHz (PC2-4200). Both performed worse than the original DDR specification due to higher latency, which made total access times longer. However, the original DDR technology tops out at speeds around 266 MHz (533 MHz effective). Faster DDR chips exist, but JEDEC has stated that they will not be standardized. These modules are mostly manufacturer optimizations of highest-yielding chips, drawing significantly more power than slower-clocked modules, and usually do not offer much, if any, greater real-world performance.
DDR2 started to become competitive with the older DDR standard by the end of 2004, as modules with lower latencies became available.[2]
Backwards compatibility
DDR2 DIMMs are not designed to be backwards compatible with DDR DIMMs. The notch on DDR2 DIMMs is in a different position than DDR DIMMs, and the pin density is slightly higher than DDR DIMMs. DDR2 is a 240-pin module, DDR is a 184-pin module.
Faster DDR2 DIMMs though, are compatible with slower DDR2 DIMMs. The memory would just run at the slower speed. Using slower DDR2 memory in a system capable of higher speeds results in the bus running at the speed of the slowest memory in use.
Relation to GDDR memory
The first commercial product to claim using the "DDR2" technology was the NVIDIA GeForce FX 5800 graphics card. However, it is important to note that this GDDR-2 memory used on graphics cards is not DDR2 per se, but rather an early midpoint between DDR and DDR2 technologies. Using "DDR2" to refer to GDDR-2 is a colloquial misnomer. In particular, the performance-enhancing doubling of the I/O clock rate is missing. It had severe overheating issues due to the nominal DDR voltages. ATI has since designed the GDDR technology further into GDDR3, which is more true to the DDR2 specifications, though with several additions suited for graphics cards.
GDDR3 is now commonly used in modern video cards. However, further confusion has been added to the mix with the appearance of budget and mid-range graphics cards which claim to use "DDR2". These cards actually use standard DDR2 chips designed for use as main system memory. These chips cannot achieve the clock speeds that GDDR3 can but are inexpensive enough to be used as memory on mid-range cards.
See also
References
- Razak Mohammed Ali. "DDR2 SDRAM interfaces for next-gen systems" (PDF). Electronic Engineering Times.
- "JESD79-2C: DDR2 SDRAM specification" (PDF). JEDEC Solid State Technology Association. May 2006. Retrieved 2007-10-07.
- "JEDEC Standard No. 21C: 4.20.13 240-Pin PC-3200/PC2-4200/PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification" (PDF). JEDEC Solid State Technology Association. January 5, 2005. Retrieved 2007-10-07.
- Ilya Gavrichenkov. "DDR2 vs. DDR: Revenge gained". X-bit Laboratories.
- Raj Mahajan. "Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2" (PDF). MemCore Inc www.memcoreinc.com.